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AD5381
I
2
C SERIAL INTERFACE TIMING
Table 7. DV
DD
= 2.7 V to 5.5 V; AV
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
T
MIN
to T
MAX
, unless otherwise noted
Parameter
1
,
2
Limit at T
MIN
, T
MAX
Unit
F
SCL
400
kHz max
t
1
2.5
μs min
t
2
0.6
μs min
t
3
1.3
μs min
t
4
0.6
μs min
t
5
100
ns min
t
63
0.9
μs max
0
μs min
t
7
0.6
μs min
t
8
0.6
μs min
t
9
1.3
μs min
t
10
300
ns max
0
ns min
t
11
300
ns max
0
ns min
300
ns max
20 + 0.1C
b
4
ns min
C
b
400
pF max
Rev. A | Page 10 of 36
Description
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD,STA
, start/repeated start condition hold time
t
SU,DAT
, data setup time
t
HD,DAT
, data hold time
t
HD,DAT
, data hold time
t
SU,STA
, setup time for repeated start
t
SU,STO
, stop condition setup time
t
BUF
, bus free time between a STOP and a START condition
t
R
, rise time of SCL and SDA when receiving
t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
F
, fall time of SDA when transmitting
t
F
, fall time of SDA when receiving (CMOS compatible)
t
F
, fall time of SCL and SDA when receiving
t
F
, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1
Guaranteed by design and characterization, not production tested.
2
See
Figure 6.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4
C
b
is the total capacitance, in pF, of one bus line. t
R
and t
F
are measured between 0.3DV
DD
and 0.7DV
DD
.
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
9
t
3
t
1
t
11
t
4
t
10
t
4
t
5
t
7
t
6
t
8
t
2
SDA
SCL
0
Figure 6. I
2
C Compatible Serial Interface Timing Diagram
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